| 87 | -- | 92 | Chua-Chin Wang, Chia-Hao Hsu, Gang-Neng Sung, Yu-Cheng Lu. A Signed Array Multiplier with Bypassing Logic |
| 93 | -- | 98 | Yun-Parn Thomas Lee. System Comparison of Electronic and Optical Correlator |
| 99 | -- | 104 | Fabian Angarita, Trinidad Sansaloni, María José Canet, Javier Valls. Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes |
| 105 | -- | 111 | Chi-Sing Leung, Ping-Man Lam, Peter Wai-Ming Tsang, Wuchao Situ. A Graphics Processing Unit Accelerated Genetic Algorithm for Affine Invariant Matching of Broken Contours |
| 113 | -- | 119 | Anissa Mokraoui, Vianney Muñoz-Jiménez, Jean Pierre Astruc. Motion Estimation Based on Spline Interpolation in H.264/AVC Video Coder for Videoconferencing Application: Performance Versus Computation Load |
| 121 | -- | 127 | Yu-Ming Lee, Yinyi Lin. Asymptotic Computation in Mode Decision for H.264/AVC Inter Frame Coding |
| 129 | -- | 134 | Erdal Oruklu, Xin Xiao, Jafar Saniie. Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors |
| 135 | -- | 139 | Lin Wang 0009, Fuliang Yin, Zhe Chen. An Improved Floating-to-Fixed-Point Conversion Scheme for DCT Quantization Algorithm |
| 141 | -- | 146 | Jeich Mar, Chi-Cheng Kuo, Shih-Hao Chou. FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System |
| 147 | -- | 152 | Juan Antonio Gómez Pulido, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez. High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications |
| 153 | -- | 189 | Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López. FPGA-based Personal Authentication Using Fingerprints |
| 191 | -- | 221 | Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López. Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications |