Journal: VLSI Signal Processing

Volume 9, Issue 3

151 -- 0Benjamin W. Wah. Guest editor s introduction
153 -- 165Dominique Lavenier, Frédéric Raimbault, Patrice Frison. I/O and computation overlap on SIMD systolic arrays
181 -- 191K Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.. Parallel reduced area multipliers
193 -- 209Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin. Digit pipelined arithmetic on fine-grain array processors
211 -- 232Ramaswamy Govindarajan, Guang R. Gao. Rate-optimal schedule for multi-rate DSP computations
233 -- 255Wee-Chiew Tan, Teresa H. Y. Meng. A low-power high performance polygon renderer for computer graphics
257 -- 273Paolo Ienne, Marc A. Viredaz. GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Volume 9, Issue 1-2

5 -- 6Ingrid Verbauwhede, Jan M. Rabaey. Guest editor s introduction design environments for DSP
7 -- 21José Luis Pino, Soonhoi Ha, Edward A. Lee, Joseph T. Buck. Software synthesis for DSP using ptolemy
23 -- 47Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala. DSP design tool requirements for embedded systems: A telecommunications industrial perspective
49 -- 65Gert Goossens, Dirk Lanneer, Marc Pauwels, Francis Depuydt, Koen Schoofs, Augusli Kifli, Marco Cornero, Paolo Petroni, Francky Catthoor, Hugo De Man. Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures
67 -- 88Ingrid Verbauwhede, Jan M. Rabaey. Synthesis for real time systems: Solutions and challenges
89 -- 104Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf. PHIDEO: High-level synthesis for high throughput applications
105 -- 119Phillip Duncan, Ken Kindsfater, Lynette Liu, Rajeev Jain. Strategies for design automation of high speed digital filters
121 -- 143Keshab K. Parhi. High-level algorithm and architecture transformations for DSP synthesis