Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi. Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. In 2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020. pages 1-3, IEEE, 2020. [doi]
Abstract is missing.