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System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

Karthik Chandrasekar 0001, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens. System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 236-241, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]

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Karthik Chandrasekar 0001

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Christian Weis

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Benny Akesson

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Norbert Wehn

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Kees Goossens

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