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Transistor-Level Analysis of Dynamic Delay Models

Jürgen Maier 0002, Matthias Függer, Thomas Nowak, Ulrich Schmid 0001. Transistor-Level Analysis of Dynamic Delay Models. In 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019. pages 76-85, IEEE, 2019. [doi]

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