Abstract is missing.
- AMC: An Asynchronous Memory CompilerSamira Ataei, Rajit Manohar. 1-8 [doi]
- Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase HandshakingAdrian Mardari, Zuzana Jelcicová, Jens Sparsø. 9-18 [doi]
- Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous CircuitsYi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang. 19-26 [doi]
- A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFETMatthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany. 27-35 [doi]
- A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake ProtocolsMackenzie J. Wibbels, Shomit Das, Dheeraj Singh Takur, Venkata Nori, Kenneth S. Stevens. 36-45 [doi]
- Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC BackboneYvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan. 46-47 [doi]
- ASIE: An Asynchronous SNN Inference Engine for AER Events ProcessingZiyang Kang, Lei Wang, Shasha Guo, Rui Gong, Yu Deng, Qiang Dou. 48-57 [doi]
- AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous TechnologyMickael Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence. 58-59 [doi]
- Synthesis from Waveform Transition GraphsAlberto Moreno, Danil Sokolov, Jordi Cortadella. 60-67 [doi]
- Asynchronous Signalling ProcessesRajit Manohar, Yoram Moses. 68-75 [doi]
- Transistor-Level Analysis of Dynamic Delay ModelsJürgen Maier 0002, Matthias Függer, Thomas Nowak, Ulrich Schmid 0001. 76-85 [doi]
- From Signal Transition Graphs to Timing Closure: Application to Bundled-Data CircuitsGrégoire Gimenez, Jean Simatic, Laurent Fesquet. 86-95 [doi]
- Verifying Timed, Asynchronous Circuits using ACL2Yan Peng, Mark R. Greenstreet. 96-104 [doi]
- A Hierarchical Approach to Self-Timed Circuit VerificationCuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland. 105-113 [doi]
- Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA ToolsMarcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans. 114-123 [doi]
- Efficient Metastability Characterization for Schmitt-TriggersJürgen Maier 0002, Andreas Steininger. 124-133 [doi]
- Hardware Trojan Insertion and Detection in Asynchronous CircuitsKoutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai. 134-143 [doi]