A. K. B. A ain, A. H. Bratt, A. P. Dorey. Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 239-242, IEEE Computer Society, 1995. [doi]
@inproceedings{AainBD95,
title = {Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique},
author = {A. K. B. A ain and A. H. Bratt and A. P. Dorey},
year = {1995},
doi = {10.1109/ICVD.1995.512116},
url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512116},
tags = {testing},
researchr = {https://researchr.org/publication/AainBD95},
cites = {0},
citedby = {0},
pages = {239-242},
booktitle = {8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India},
publisher = {IEEE Computer Society},
}