VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input - researchr publication

researchr

You are not signed in
Sign in
Sign up

Soroush Abbaspour, Hanif Fatemi, Massoud Pedram. VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. In John Lach, Gang Qu, Yehea I. Ismail, editors, Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005. pages 426-430, ACM, 2005. [doi]

Abstract is missing.

runs on WebDSL