A 1.2V CMOS multiplier for 10 Gbit/s equalization

Justin P. Abbott, Calvin Plett, John W. M. Rogers. A 1.2V CMOS multiplier for 10 Gbit/s equalization. In Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët, editors, Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. pages 379-382, IEEE, 2005. [doi]

@inproceedings{AbbottPR05-1,
  title = {A 1.2V CMOS multiplier for 10 Gbit/s equalization},
  author = {Justin P. Abbott and Calvin Plett and John W. M. Rogers},
  year = {2005},
  doi = {10.1109/ESSCIR.2005.1541639},
  url = {https://doi.org/10.1109/ESSCIR.2005.1541639},
  researchr = {https://researchr.org/publication/AbbottPR05-1},
  cites = {0},
  citedby = {0},
  pages = {379-382},
  booktitle = {Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005},
  editor = {Laurent Fesquet and Andreas Kaiser and Sorin Cristoloveanu and Michel Brillouët},
  publisher = {IEEE},
  isbn = {0-7803-9205-1},
}