A double data rate 8T-cell SRAM architecture for systems-on-chip - researchr publication authors

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Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross. A double data rate 8T-cell SRAM architecture for systems-on-chip. In 2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012. pages 1-4, IEEE, 2012. [doi]

This author has not been identified. Look up 'Saleh Abdel-Hafeez' in GoogleThis author has not been identified. Look up 'Mohammad Shatnawi' in GoogleThis author has not been identified. Look up 'Ann Gordon-Ross' in Google

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