Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross. A double data rate 8T-cell SRAM architecture for systems-on-chip. In 2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012. pages 1-4, IEEE, 2012. [doi]
@inproceedings{Abdel-HafeezSG12,
title = {A double data rate 8T-cell SRAM architecture for systems-on-chip},
author = {Saleh Abdel-Hafeez and Mohammad Shatnawi and Ann Gordon-Ross},
year = {2012},
doi = {10.1109/ISSoC.2012.6376347},
url = {http://dx.doi.org/10.1109/ISSoC.2012.6376347},
researchr = {https://researchr.org/publication/Abdel-HafeezSG12},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012},
publisher = {IEEE},
isbn = {978-1-4673-2895-1},
}