Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets

Nabil M. Abdulrazzaq, Sandeep K. Gupta. Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. In 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA. pages 186-196, IEEE Computer Society, 2003. [doi]

@inproceedings{AbdulrazzaqG03,
  title = {Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets},
  author = {Nabil M. Abdulrazzaq and Sandeep K. Gupta},
  year = {2003},
  url = {http://csdl.computer.org/comp/proceedings/vts/2003/1924/00/19240186abs.htm},
  tags = {testing},
  researchr = {https://researchr.org/publication/AbdulrazzaqG03},
  cites = {0},
  citedby = {0},
  pages = {186-196},
  booktitle = {21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-1924-5},
}