Efficient Designs for Adder Comparator

Hisako Adachi, Shinji Nakamura. Efficient Designs for Adder Comparator. In Proceedings of the 41st Annual Conference on Information Sciences and Systems, CISS 2007, 14-16 March 2007, Johns Hopkins University, Department of Electrical Engineering, Baltimore, MD, USA. pages 754, IEEE, 2007. [doi]

Authors

Hisako Adachi

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Shinji Nakamura

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