Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh. On Minimization of Test Application Time for RAS. In VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010. pages 393-398, IEEE, 2010. [doi]
@inproceedings{AdigaASSFS10, title = {On Minimization of Test Application Time for RAS}, author = {Raghavendra Adiga and Gandhi Arpit and Virendra Singh and Kewal K. Saluja and Hideo Fujiwara and Adit D. Singh}, year = {2010}, doi = {10.1109/VLSI.Design.2010.61}, url = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.61}, tags = {testing}, researchr = {https://researchr.org/publication/AdigaASSFS10}, cites = {0}, citedby = {0}, pages = {393-398}, booktitle = {VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010}, publisher = {IEEE}, isbn = {978-0-7695-3928-7}, }