Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita. An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM). J. Solid-State Circuits, 35(11):1668-1672, 2000. [doi]
Abstract is missing.