An architecture for synthesis of testable finite state machines

Vishwani D. Agrawal, Kwang-Ting Cheng. An architecture for synthesis of testable finite state machines. In Gordon Adshead, Jochen A. G. Jess, editors, European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990. pages 612-616, IEEE Computer Society, 1990. [doi]

Abstract

Abstract is missing.