Design for built-in FPGA reliability via fine-grained 2-D error correction codes

A. Ahilan, P. Deepa. Design for built-in FPGA reliability via fine-grained 2-D error correction codes. Microelectronics Reliability, 55(9-10):2108-2112, 2015. [doi]

@article{AhilanD15,
  title = {Design for built-in FPGA reliability via fine-grained 2-D error correction codes},
  author = {A. Ahilan and P. Deepa},
  year = {2015},
  doi = {10.1016/j.microrel.2015.06.075},
  url = {http://dx.doi.org/10.1016/j.microrel.2015.06.075},
  researchr = {https://researchr.org/publication/AhilanD15},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Reliability},
  volume = {55},
  number = {9-10},
  pages = {2108-2112},
}