Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs

Ali Ahmadi, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris. Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs. In 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016. pages 1-6, IEEE Computer Society, 2016. [doi]

@inproceedings{AhmadiNOPM16,
  title = {Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs},
  author = {Ali Ahmadi and Amit Nahar and Bob Orr and Michael Pas and Yiorgos Makris},
  year = {2016},
  doi = {10.1109/VTS.2016.7477263},
  url = {http://doi.ieeecomputersociety.org/10.1109/VTS.2016.7477263},
  researchr = {https://researchr.org/publication/AhmadiNOPM16},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4673-8454-4},
}