Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske. Buffered Interconnects in 3D IC Layout Design. In Baris Taskin, Tsung-Yi Ho, editors, Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016. ACM, 2016. [doi]
@inproceedings{AhmedMC16,
title = {Buffered Interconnects in 3D IC Layout Design},
author = {Mohammad A. Ahmed and Sucheta Mohapatra and Malgorzata Chrzanowska-Jeske},
year = {2016},
doi = {10.1145/2947357.2947366},
url = {http://doi.acm.org/10.1145/2947357.2947366},
researchr = {https://researchr.org/publication/AhmedMC16},
cites = {0},
citedby = {0},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016},
editor = {Baris Taskin and Tsung-Yi Ho},
publisher = {ACM},
isbn = {978-1-4503-4430-2},
}