Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske. Buffered Interconnects in 3D IC Layout Design. In Baris Taskin, Tsung-Yi Ho, editors, Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016. ACM, 2016. [doi]
Abstract is missing.