Yoni Aizik, Avinoam Kolodny. Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. VLSI Design, 2011, 2011. [doi]
@article{AizikK11,
title = {Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints},
author = {Yoni Aizik and Avinoam Kolodny},
year = {2011},
doi = {10.1155/2011/845957},
url = {http://dx.doi.org/10.1155/2011/845957},
researchr = {https://researchr.org/publication/AizikK11},
cites = {0},
citedby = {0},
journal = {VLSI Design},
volume = {2011},
}