Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating

Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa. Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ T. on System LSI Design Methodology, 7:74-80, 2014. [doi]

Abstract

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