A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier

Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura. A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011. pages 293-296, IEEE, 2011. [doi]

Abstract

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