Design of a 32-bit squarer - exploiting addition redundancy

Asim J. Al-Khalili, Aiping Hu. Design of a 32-bit squarer - exploiting addition redundancy. In ISCAS (5). pages 325-328, 2003. [doi]

@inproceedings{Al-KhaliliH03,
  title = {Design of a 32-bit squarer - exploiting addition redundancy},
  author = {Asim J. Al-Khalili and Aiping Hu},
  year = {2003},
  doi = {10.1109/ISCAS.2003.1206269},
  url = {http://dx.doi.org/10.1109/ISCAS.2003.1206269},
  tags = {redundancy, design},
  researchr = {https://researchr.org/publication/Al-KhaliliH03},
  cites = {0},
  citedby = {0},
  pages = {325-328},
  booktitle = {ISCAS (5)},
}