Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm

Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido. Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012. pages 63-68, IEEE, 2012. [doi]

@inproceedings{Algredo-BadilloMUC12,
  title = {Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm},
  author = {Ignacio Algredo-Badillo and Miguel Morales-Sandoval and Claudia Feregrino Uribe and René Cumplido},
  year = {2012},
  doi = {10.1109/ISVLSI.2012.63},
  url = {http://dx.doi.org/10.1109/ISVLSI.2012.63},
  researchr = {https://researchr.org/publication/Algredo-BadilloMUC12},
  cites = {0},
  citedby = {0},
  pages = {63-68},
  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-2234-8},
}