Table of Contents

• A Dataflow Framework for DSP Algorithm RefinementYoungsoo Kim, Winser E. Alexander, William W. Edmonson. 1-2 [doi]
• Impact of Logic Synthesis on Soft Error Rate of Digital Integrated CircuitsDaniel B. Limbrick. 3-4 [doi]
• Design, Synthesis and Test of Reversible Circuits for Emerging NanotechnologiesHimanshu Thapliyal, Nagarajan Ranganathan. 5-6 [doi]
• Algorithms for On-Chip Solution Preparation Using Digital Microfluidic BiochipsSudip Roy, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya. 7-8 [doi]
• A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected TopologiesMaryam Bahmani, Abbas Sheibanyrad, Frédéric Pétrot, Florentine Dubois, Paolo Durante. 9-14 [doi]
• Formal Estimation of Worst-Case Communication Latency in a Network-on-ChipVinitha Arakkonam Palaniveloo, Arcot Sowmya. 15-20 [doi]
• Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and UpgradeabilityMarios Evripidou, Chrysostomos Nicopoulos, Vassos Soteriou, Jongman Kim. 21-26 [doi]
• A Fast Head-Tail Expression Generator for TCAM - Application to Packet ClassificationInfall Syafalni, Tsutomu Sasao. 27-32 [doi]
• Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVsBing Shi, Ankur Srivastava, Avram Bar-Cohen. 33-38 [doi]
• Adaptive Stackable 3D Cache Architecture for ManycoresEric Guthmuller, Ivan Miro Panades, Alain Greiner. 39-44 [doi]
• Reducing Temperature Variation in 3D Integrated Circuits Using Heat PipesKunal P. Ganeshpure, Sandip Kundu. 45-50 [doi]
• A Temperature and Reliability Oriented Simulation Framework for Multi-core ArchitecturesSimone Corbetta, Davide Zoni, William Fornaciari. 51-56 [doi]
• Hardware Comparison of the ISO/IEC 29192-2 Block CiphersNeil Hanley, Máire O'Neill. 57-62 [doi]
• Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash AlgorithmIgnacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido. 63-68 [doi]
• VLSI Design and Implementation of Homophonic Security SystemNicolas Sklavos, Paris Kitsos, Odysseas G. Koufopavlou. 69-72 [doi]
• Understanding the Switching Mechanism in Transition Metal Oxide Based ReRAM DevicesRashmi Jha, Branden Long. 73-77 [doi]
• Operation Dynamics in Phase-Change Memory Cells and the Role of Access DevicesAzer Faraclas, Nicholas E. Williams, Faruk Dirisaglik, Kadir Cil, Ali Gokirmak, Helena Silva. 78-83 [doi]
• Nano-PPUF: A Memristor-Based Security PrimitiveJeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak. 84-87 [doi]
• RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA)Ganesh Khedkar, Dhireesha Kudithipudi. 88-93 [doi]
• Synthesis of Multithreshold Threshold GatesMaciej Nikodem, Marek A. Bawiec, Janusz Biernat. 94-99 [doi]
• An Improvement in Partial Order Reduction Using Behavioral AnalysisYingying Zhang, Emmanuel Rodriguez, Hao Zheng 0001, Chris J. Myers. 100-107 [doi]
• A DFT Methodology for Repairing Embedded Memories of Large MPSoCsKunal P. Ganeshpure, Sandip Kundu. 108-113 [doi]
• Binary Difference Based Test Data Compression for NoC Based SoCsSanga Chaki, Chandan Giri, Hafizur Rahaman. 114-119 [doi]
• On Design of Low Cost Power Supply Noise Detection Sensor for MicroprocessorsArunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu. 120-125 [doi]
• A Tuneable CMOS Pulse Generator for Detecting the Cracks in Concrete WallsTrivikrama Rao, Ashudeb Dutta, Shiv Govind Singh, Arijit De, Bhibu Dutta Sahoo. 126-130 [doi]
• A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS TechnologyXuelian Liu, John F. McDonald. 131-134 [doi]
• Design of Quantum Circuits for Random Walk AlgorithmsAmlan Chakrabarti, ChiaChun Lin, Niraj K. Jha. 135-140 [doi]
• An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA TechnologiesMahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty. 141-146 [doi]
• A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular AutomataMohsen M. Arjmand, Mohsen Soryani, Keivan Navi, Mohammad A. Tehrani. 147-152 [doi]
• Ultra Low Power Circuit Design Using Tunnel FETsRavindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan. 153-158 [doi]
• Protecting CRT RSA against Fault and Power Side Channel AttacksApostolos P. Fournaris, Odysseas G. Koufopavlou. 159-164 [doi]
• On Design of Temperature Invariant Physically Unclonable Functions Based on Ring OscillatorsRaghavan Kumar, Vinay C. Patil, Sandip Kundu. 165-170 [doi]
• Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable FunctionsDomenic Forte, Ankur Srivastava. 171-176 [doi]
• A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve CryptosystemsYuejian Fang, Zhonghai Wu. 177-182 [doi]
• Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale CircuitsHong Luo, Yu Wang 0002, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang. 183-188 [doi]
• RAEF: A Power Normalized System-Level Reliability Analysis and Estimation FrameworkRishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 189-194 [doi]
• Aging-Aware Instruction Cache Design by Duty Cycle BalancingTao Jin, Shuai Wang. 195-200 [doi]
• Design of Prefix-Based Optimal Reversible ComparatorChetan Vudadha, Sai Phaneendra P., Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas. 201-206 [doi]
• Mach-Zehnder Interferometer Based All Optical Reversible NOR GatesSaurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan. 207-212 [doi]
• Circuit Line Minimization in the HDL-Based Synthesis of Reversible LogicRobert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler. 213-218 [doi]
• Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics PrinciplesMatthew Morrison, Nagarajan Ranganathan. 219-224 [doi]
• Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid AddersChetan Vudadha, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas. 225-230 [doi]
• Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic StructureMatthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan. 231-236 [doi]
• Data-Width-Driven Power Gating of Integer Arithmetic CircuitsTung Thanh Hoang, Per Larsson-Edefors. 237-242 [doi]
• Uncertain Model and Algorithm for Hardware/Software PartitioningYu Jiang, Hehua Zhang, Xun Jiao, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun. 243-248 [doi]
• Instruction Set Architecture Extensions for a Dynamic Task Scheduling UnitOliver Arnold, Benedikt Noethen, Gerhard Fettweis. 249-254 [doi]
• SCOC IP Cores for Custom Built Supercomputing NodesNagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Vigneshwaran Sankaran, Bharanidharan Vasudevan, Ravindhiran Mukundrajan, Nachiappan Chidambaram Nachiappan, Aswin Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, Vignesh Veppur Sankaranarayanan. 255-260 [doi]
• A Hardware Architecture for Image Clustering Using Spiking Neural NetworksMarco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Héctor Hugo Avilés-Arriaga, Yahir Hernandez-Mier, Miguel Morales-Sandoval. 261-266 [doi]
• Compilation Accelerator on SiliconNagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan P. Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. S. Vignesh, Ravindhiran Mukundrajan. 267-272 [doi]
• Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical ApplicationsGeng Zheng, Saraju P. Mohanty, Elias Kougianos. 273-278 [doi]
• Variance Optimization of CMOS OpAmp Performances Using Experimental Design ApproachArnab Khawas, Siddhartha Mukhopadhyay. 279-284 [doi]
• Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor DesignOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Geng Zheng. 285-290 [doi]
• Methodology for Efficient Multi-threading of Parsers in EDA ToolsPrakash Shanbhag, Chandramouli Gopalakrishnan, Saibal Ghosh. 291-296 [doi]
• A Case Study in Developing an Efficient Multi-threaded EDA Parser: Synopsys SDF ParserPrakash Shanbhag, Chandramouli Gopalakrishnan, Saibal Ghosh. 297-301 [doi]
• Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJsLuca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki. 302-307 [doi]
• 0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSITakahiro Watanabe, Minoru Watanabe. 308-313 [doi]
• On-Chip Sample Preparation with Multiple Dilutions Using Digital MicrofluidicsDebasis Mitra, Sudip Roy, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 314-319 [doi]
• A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic BiochipsPranab Roy, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta. 320-325 [doi]
• Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS CircuitsOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos. 326-331 [doi]
• Parametric Hierarchy Recovery in Layout Extracted NetlistsJohn Lee, Puneet Gupta, Fedor Pikus. 332-337 [doi]
• Soft-Error Probability Due to SET in Clock Tree NetworksRaul Chipana, Eduardo Chielle, Fernanda Lima Kastensmidt, Jorge Tonfat, Ricardo Reis. 338-343 [doi]
• Delay Analysis for an N-Input Current Mode Threshold Logic GateChandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas. 344-349 [doi]
• Testing of Trusted CMOS Data ConvertersAshok Srivastava, Rajiv Soundararajan. 350-355 [doi]
• Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi. 356-361 [doi]
• A Novel Design of Secure and Private CircuitsMahadevan Gomathisankaran, Akhilesh Tyagi. 362-367 [doi]
• A Survey of Microarchitecture Support for Embedded Processor SecurityArun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, Sateesh Addepalli. 368-373 [doi]
• Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache DesignXiuyuan Bi, Hai Li, Jae-Joon Kim. 374-379 [doi]
• PTL: PCM Translation LayerZili Shao, Naehyuck Chang, Nikil Dutt. 380-385 [doi]
• A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory SystemsHyung Gyu Lee, Seungcheol Baek, Jongman Kim, Chrysostomos Nicopoulos. 386-391 [doi]
• NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile MemoriesMatthew Poremba, Yuan Xie. 392-397 [doi]
• Utilizing PCM for Energy Optimization in Embedded SystemsZili Shao, Yongpan Liu, Yiran Chen, Tao Li. 398-403 [doi]
• Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access CharacteristicsYong Li 0009, Alex K. Jones. 404-409 [doi]
• Code Motion for Migration Minimization in STT-RAM Based Hybrid CacheQing'an Li, Liang Shi, Jianhua Li, Chun Jason Xue, Yanxiang He. 410-415 [doi]