A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors

Hananeh Aliee, Hamid R. Zarandi. A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors. In Francesco Flammini, Sandro Bologna, Valeria Vittorini, editors, Computer Safety, Reliability, and Security - 30th International Conference, SAFECOMP 2011, Naples, Italy, September 19-22, 2011. Proceedings. Volume 6894 of Lecture Notes in Computer Science, pages 324-337, Springer, 2011. [doi]

Abstract

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