Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm

Abdallah Alma'aitah, Zine-Eddine Abid. Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm. In Yervant Zorian, Imtinan Elahi, André Ivanov, Ashraf Salem, editors, 5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010. pages 31-36, IEEE, 2010. [doi]

Abstract

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