Abstract is missing.
- An automated design methodology for stress avoidance in analog & mixed signal designsRomany Sameer, Ahmed Nader Mohieldin, Haitham Eissa. 3-7 [doi]
- Improving timing characteristics through Semi-Random Net ReorderingBassel Soudan. 8-12 [doi]
- A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designsRami F. Salem, Abdelrahman ElMously, Haitham Eissa, Mohamed Dessouky, Mohab H. Anis. 13-17 [doi]
- Voltage island design in multi-core SIMD processorsSohaib Majzoub. 18-23 [doi]
- High speed low power composite field SBOXLamiaa A. Elazm, Magdy A. El-Moursy, Hamed Elsimary, Moawad I. Dessouky, Farid Shawki. 24-27 [doi]
- Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nmAbdallah Alma'aitah, Zine-Eddine Abid. 31-36 [doi]
- Design and implementation of low latency network interface for network on chipBrahim Attia, Wissem Chouchene, Abdelkrim Zitouni, Abid Nourdin, Rached Tourki. 37-42 [doi]
- Soft-core reduction methodology for SIMD architecture: OPENRISC case studyBouthaina Dammak, Mouna Baklouti, Mohamed Abid. 43-48 [doi]
- ECC design for fault-tolerant crossbar memories: A case studyNor Zaidi Haron, Said Hamdioui, Zaiyan Ahyadi. 61-66 [doi]
- On NOR-2 von Neumann multiplexingWalid Ibrahim, Valeriu Beiu, Azam Beg. 67-72 [doi]
- A design for reliability methodology based on selective overdesignSyed Askari, Mehrdad Nourani. 73-77 [doi]
- Cost-free low-power test in compression-based reconfigurable scan designsSobeeh Almukhaizim, Mohammad Gh. Mohammad, Eman AlQuraishi. 78-82 [doi]
- Routability driven placement for mesh-based FPGA architectureMariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez. 85-90 [doi]
- Reconfigurable low-power Concurrent Error Detection in logic circuitsSobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu. 91-96 [doi]
- Prediction performance method for dynamic task scheduling, case study: the OLLAF ArchitectureIsmail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid. 97-102 [doi]
- A novel conflict directed jumping algorithm for hardware-based SAT solversMona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem. 103-108 [doi]
- Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failuresH. A. Abdel-Aziz, M. M. Abdel-Aziz, A. G. Wassal, A. A. Abou-Auf. 117-121 [doi]
- Identification of IR-drop hot-spots in defective power distribution network using TDF ATPGJunxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim. 122-127 [doi]
- MBIST architecture framework based on orthogonal constructsA. J. van de Goor, Said Hamdioui. 128-133 [doi]
- Parasitic memory effect in CMOS SRAMsSandra Irobi, Zaid Al-Ars, Michel Renovell. 134-139 [doi]
- Hierarchical synthesis of reversible circuits using positive and negative Davio decompositionMathias Soeken, Robert Wille, Rolf Drechsler. 143-148 [doi]
- SAT-based ATPG for reversible circuitsHongyan Zhang, Robert Wille, Rolf Drechsler. 149-154 [doi]
- Performance and bandwidth optimization for biological sequence alignmentLaiq Hasan, Zaid Al-Ars, Mottaqiallah Taouil, Koen Bertels. 155-160 [doi]
- Mapping SMV models to event-B modelsSamah Hassan, Mohamed Taher, Ayman M. Wahba. 161-166 [doi]