High performance analog and digital PLL design

T. M. Almaida, Moisés S. Piedade. High performance analog and digital PLL design. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 394-397, IEEE, 1999. [doi]

@inproceedings{AlmaidaP99,
  title = {High performance analog and digital PLL design},
  author = {T. M. Almaida and Moisés S. Piedade},
  year = {1999},
  doi = {10.1109/ISCAS.1999.780025},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1999.780025},
  tags = {design},
  researchr = {https://researchr.org/publication/AlmaidaP99},
  cites = {0},
  citedby = {0},
  pages = {394-397},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA},
  publisher = {IEEE},
  isbn = {0-7803-5471-0},
}