The following publications are possibly variants of this publication:
- A novel design of a memristor-based look-up table (LUT) for FPGAT. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi. apccas 2014: 703-706 [doi]
- Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAsT. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi. integration, 55:1-11, 2016. [doi]
- Delay Minimal Mapping of RTL Structures onto LUT Based FPGAsA. R. Naseer, M. Balakrishnan, Anshul Kumar. fpl 1995: 139-148
- Direct mapping of RTL structures onto LUT-based FPGA sA. R. Naseer, M. Balakrishnan, Anshul Kumar. tcad, 17(7):624-631, 1998. [doi]
- Operational fault detection and monitoring of a memristor-based LUTT. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi. date 2015: 429-434 [doi]