Bottom-up digital system-level reliability modeling

N. Ruiz Amador, V. Huard, E. Pion, F. Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, L. Anghel. Bottom-up digital system-level reliability modeling. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]

Authors

N. Ruiz Amador

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V. Huard

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E. Pion

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F. Cacho

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Damien Croain

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V. Robert

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Sylvain Engels

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Philippe Flatresse

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L. Anghel

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