Three Dimensional FPGA Architecture with Fewer TSVs

Motoki Amagasaki, Masato Ikebe, Qian Zhao 0001, Masahiro Iida, Toshinori Sueyoshi. Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Transactions, 101-D(2):278-287, 2018. [doi]

@article{AmagasakiIZIS18,
  title = {Three Dimensional FPGA Architecture with Fewer TSVs},
  author = {Motoki Amagasaki and Masato Ikebe and Qian Zhao 0001 and Masahiro Iida and Toshinori Sueyoshi},
  year = {2018},
  url = {http://search.ieice.org/bin/summary.php?id=e101-d_2_278},
  researchr = {https://researchr.org/publication/AmagasakiIZIS18},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {101-D},
  number = {2},
  pages = {278-287},
}