Omar Amin, Youssef Ramzy, Omar Ibrahem, Ahmed Fouad, Khaled Mohamed, Mohamed AbdElSalam. System Verilog Assertions Synthesis Based Compiler. In 17th International Workshop on Microprocessor and SOC Test and Verification, MTV 2016, Austin, TX, USA, December 12-13, 2016. pages 65-70, IEEE Computer Society, 2016. [doi]
Abstract is missing.