Abstract is missing.
- Fake CPU: A Flexible and Simulation Cost-Effective UVC for Testing Shared CachesSaddam Jamil Quirem, Prasad Krishna Saravu. 1-6 [doi]
- Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency CheckerPrasad Krishna Saravu. 7-14 [doi]
- Formal Based Methodology for Inferring Memory Mapped RegistersHaytham Saafan, M. Watheq El-Kharashi, Ashraf Salem. 15-18 [doi]
- A Case Study: Pre-Silicon SoC RAS Validation for NoC Server ProcessorSenwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak. 19-24 [doi]
- Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction DebuggingVibarajan Viswanathan, Juliet Runhaar, Doug Reed, Jun Zhao. 25-29 [doi]
- Coverage Closure Efficient UVM Based Generic Verification Architecture for Flash Memory ControllersAhmed El-Yamany, Sameh El-Ashry, Khaled Salah. 30-34 [doi]
- Automatic RTL-to-Formal Code Converter for IP Security Formal VerificationXiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin. 35-38 [doi]
- 2.5D/3D Integration Technologies for Circuit ObfuscationYang Xie, Chongxi Bao, Yuntao Liu, Ankur Srivastava. 39-44 [doi]
- Hardware-Based Workload Forensics and Malware Detection in MicroprocessorsLiwei Zhou, Yiorgos Makris. 45-50 [doi]
- Towards Property Driven Hardware SecurityWei Hu, Alric Althoff, Armita Ardeshiricham, Ryan Kastner. 51-56 [doi]
- An Efficient Scenario Based Testing Methodology Using UVMKhaled Fathy, Khaled Salah. 57-60 [doi]
- Transaction Level Power Modeling (TLPM) MethodologyAmr B. Darwish, Magdy A. El-Moursy, Mohamed Dessouky. 61-64 [doi]
- System Verilog Assertions Synthesis Based CompilerOmar Amin, Youssef Ramzy, Omar Ibrahem, Ahmed Fouad, Khaled Mohamed, Mohamed AbdElSalam. 65-70 [doi]
- Scalable, Constrained Random Software Driven VerificationSainath Karlapalem, Shashank Venugopal. 71-76 [doi]
- Echoing the "Generality Concept" through the Bus Functional Model Architecture in Universal Verification EnvironmentsAhmed El-Yamany. 77-80 [doi]