A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS

Jens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, S. Tambouris, Maurits Ortmanns. A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 325-328, IEEE, 2017. [doi]

@inproceedings{Anders0DSRTO17,
  title = {A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS},
  author = {Jens Anders and Sebastian Bader 0003 and Markus Dietl and Puneet Sareen and G. Rombach and S. Tambouris and Maurits Ortmanns},
  year = {2017},
  doi = {10.1109/ASSCC.2017.8240282},
  url = {https://doi.org/10.1109/ASSCC.2017.8240282},
  researchr = {https://researchr.org/publication/Anders0DSRTO17},
  cites = {0},
  citedby = {0},
  pages = {325-328},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-3178-2},
}