Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li. A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. In 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014. pages 83-86, IEEE, 2014. [doi]
@inproceedings{AoHLWL14,
title = {A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy},
author = {Kun Ao and Yajuan He and Liang Li and Yuxin Wang and Qiang Li},
year = {2014},
doi = {10.1109/ISICIR.2014.7029486},
url = {http://dx.doi.org/10.1109/ISICIR.2014.7029486},
researchr = {https://researchr.org/publication/AoHLWL14},
cites = {0},
citedby = {0},
pages = {83-86},
booktitle = {2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014},
publisher = {IEEE},
isbn = {978-1-4799-4833-8},
}