Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang. A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
@inproceedings{AoyagiYTIONNWHC23,
title = {A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking},
author = {Yumito Aoyagi and Makoto Yabuuchi and Tomotaka Tanaka and Yuichiro Ishii and Yoshiaki Osada and Takaaki Nakazato and Koji Nii and Isabel Wang and Yu-Hao Hsu and Hong-Chen Cheng and Hung-Jen Liao and Tsung-Yung Jonathan Chang},
year = {2023},
doi = {10.23919/VLSITechnologyandCir57934.2023.10185429},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185429},
researchr = {https://researchr.org/publication/AoyagiYTIONNWHC23},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
publisher = {IEEE},
isbn = {978-4-86348-806-9},
}