Davide Appello, M. Laurino, M. Pranzo. A mathematical model to assess the influence of parallelism in a semiconductor back-end test floor. In International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017. pages 138-143, IEEE, 2017. [doi]
@inproceedings{AppelloLP17,
title = {A mathematical model to assess the influence of parallelism in a semiconductor back-end test floor},
author = {Davide Appello and M. Laurino and M. Pranzo},
year = {2017},
doi = {10.1109/ITC-ASIA.2017.8097129},
url = {https://doi.org/10.1109/ITC-ASIA.2017.8097129},
researchr = {https://researchr.org/publication/AppelloLP17},
cites = {0},
citedby = {0},
pages = {138-143},
booktitle = {International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017},
publisher = {IEEE},
isbn = {978-1-5386-3051-8},
}