Abstract is missing.
- Tutorial I: Topic: Automotive test strategiesYervant Zorian. [doi]
- Keynote I: Hardware security - Verification, test, and defense mechanismsTim Cheng. [doi]
- Low-distortion signal generation for analog/mixed-signal circuit testing with digital ATEMasayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi. 2-7 [doi]
- A quick jitter tolerance estimation technique for bang-bang CDRsYen-Long Lee, Soon-Jyh Chang. 8-13 [doi]
- Evaluation of loop transfer function based dynamic testing of LDOsMehmet Ince, Ender Yilmaz, Jae-woong Jeong, LeRoy Winemberg, Sule Ozev. 14-19 [doi]
- Test generation for open and delay faults in CMOS circuitsCheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy. 21-26 [doi]
- Cell-aware test generation time reduction by using switch-level ATPGPo-Yao Chuang, Cheng-Wen Wu, Harry H. Chen. 27-32 [doi]
- GPU-accelerated fault dictionary generation for the TRAX fault modelMatthew Beckler, R. D. Shawn Blanton. 34-39 [doi]
- Physical-aware diagnosis of multiple interconnect defectsPo-Hao Chen, Chi-Lin Lee, Jing-yu Chen, Po-Wei Chen, James Chien-Mo Li. 40-45 [doi]
- A run-pause-resume silicon debug technique for multiple clock domain systemsShuo-Lian Hong, Kuen-Jong Lee. 46-51 [doi]
- A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosabilityChih-Hao Wang, Tong-Yu Hsieh. 52-57 [doi]
- A dependable AMR sensor system for automotive applicationsAndreina Zambrano, Hans G. Kerkhoff. 59-64 [doi]
- An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependabilityHans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, Ahmed Ibrahim. 65-70 [doi]
- Symbiotic system models for efficient IGT system design and testCheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen. 71-76 [doi]
- A lightweight X-masking scheme for IoT designsDaniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen. 77-82 [doi]
- Fan-out wafer level chip scale package testingHao Chen, Hung-Chih Lin, Min-Jer Wang. 84-89 [doi]
- Testing-for-manufacturing (TFM) for ultra-thin IPD on InFOTang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang. 90-95 [doi]
- Test strategy for storage SOCsAbhishek Bhattacharya, Ramesh Tekumalla. 96-99 [doi]
- Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh powerShyue-Kung Lu, Hung-Kai Huang. 101-106 [doi]
- Software-hardware-cooperated built-in self-test scheme for channel-based DRAMsTsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou. 107-111 [doi]
- Adapting an industrial memory BIST solution for testing CAMsJais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim. 112-117 [doi]
- Trustworthy reconfigurable access to on-chip infrastructureMichael A. Kochte, Rafal Baranowski, Hans-Joachim Wunderlich. 119-124 [doi]
- On the effects of real time and contiguous measurement with a digital temperature and voltage sensorYousuke Miyake, Yasuo Sato, Seiji Kajihara. 125-130 [doi]
- Enhancing security of logic encryption using embedded key generation unitRajit Karmakar, Santanu Chattopadhyay, Rohit Kapur. 131-136 [doi]
- A mathematical model to assess the influence of parallelism in a semiconductor back-end test floorDavide Appello, M. Laurino, M. Pranzo. 138-143 [doi]
- A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cardsErik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith. 144-149 [doi]
- Test item priority estimation for high parallel test efficiency under ATE debug time constraintsYoung-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, Sungho Kang. 150-154 [doi]
- State assignment for fault tolerant stochastic computing with linear finite state machinesHideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue. 156-161 [doi]
- An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffsYi-Ju Ke, Yi-Chieh Ghen, Jng-Jer Huang. 162-167 [doi]
- Speeding up power verification by merging equivalent power domains in RTL design with UPFCharles Chia-Hao Hsu, Charles H.-P. Wen. 168-173 [doi]