Yi-Ju Ke, Yi-Chieh Ghen, Jng-Jer Huang. An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffs. In International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017. pages 162-167, IEEE, 2017. [doi]
Abstract is missing.