Optimal register allocation in high level synthesis

S. Aranake, Vijay K. Raj, M. Vashi, Hee Yong Youn. Optimal register allocation in high level synthesis. In Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993. pages 71-75, IEEE, 1993. [doi]

Authors

S. Aranake

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Vijay K. Raj

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M. Vashi

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Hee Yong Youn

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