Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS

Pramod V. Argade. Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems, 8(1):33-40, 1989. [doi]

@article{Argade89,
  title = {Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS},
  author = {Pramod V. Argade},
  year = {1989},
  doi = {10.1109/43.21816},
  url = {http://doi.ieeecomputersociety.org/10.1109/43.21816},
  researchr = {https://researchr.org/publication/Argade89},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {8},
  number = {1},
  pages = {33-40},
}