Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS

Pramod V. Argade. Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems, 8(1):33-40, 1989. [doi]

Abstract

Abstract is missing.