The following publications are possibly variants of this publication:
- MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithmJude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic. iccad 2008: 678-684 [doi]
- Multiprocessor information concealment architecture to prevent power analysis-based side channel attacksJude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic. iet-cdt, 5(1):1-15, 2011. [doi]
- DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacksJude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa. aspdac 2013: 620-625 [doi]
- Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacksJude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa. iet-cds, 7(5):283-293, 2013. [doi]