Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy. Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. In ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013. pages 415-418, IEEE, 2013. [doi]
@inproceedings{AsthanaKJNHG13,
title = {Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control},
author = {Vivek Asthana and Malathi Kar and Jean Jimenez and Jean-Philippe Noel and Sébastien Haendler and Philippe Galy},
year = {2013},
doi = {10.1109/ESSCIRC.2013.6649161},
url = {https://doi.org/10.1109/ESSCIRC.2013.6649161},
researchr = {https://researchr.org/publication/AsthanaKJNHG13},
cites = {0},
citedby = {0},
pages = {415-418},
booktitle = {ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013},
publisher = {IEEE},
isbn = {978-1-4799-0644-4},
}