A Statistical Wafer Scale Error and Redundancy Analysis Simulator

Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B. A Statistical Wafer Scale Error and Redundancy Analysis Simulator. In Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis 0001, editors, VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers. Volume 586 of IFIP Advances in Information and Communication Technology, pages 139-163, Springer, 2019. [doi]

Authors

Atishay

This author has not been identified. Look up 'Atishay' in Google

Ankit Gupta 0010

This author has not been identified. Look up 'Ankit Gupta 0010' in Google

Rashmi Sonawat

This author has not been identified. Look up 'Rashmi Sonawat' in Google

Helik Kanti Thacker

This author has not been identified. Look up 'Helik Kanti Thacker' in Google

Prasanth B

This author has not been identified. Look up 'Prasanth B' in Google