Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B. A Statistical Wafer Scale Error and Redundancy Analysis Simulator. In Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis 0001, editors, VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers. Volume 586 of IFIP Advances in Information and Communication Technology, pages 139-163, Springer, 2019. [doi]
@inproceedings{Atishay0STB19,
title = {A Statistical Wafer Scale Error and Redundancy Analysis Simulator},
author = {Atishay and Ankit Gupta 0010 and Rashmi Sonawat and Helik Kanti Thacker and Prasanth B},
year = {2019},
doi = {10.1007/978-3-030-53273-4_7},
url = {https://doi.org/10.1007/978-3-030-53273-4_7},
researchr = {https://researchr.org/publication/Atishay0STB19},
cites = {0},
citedby = {0},
pages = {139-163},
booktitle = {VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers},
editor = {Carolina Metzler and Pierre-Emmanuel Gaillardon and Giovanni De Micheli and Carlos Silva Cárdenas and Ricardo Reis 0001},
volume = {586},
series = {IFIP Advances in Information and Communication Technology},
publisher = {Springer},
isbn = {978-3-030-53273-4},
}