Hiromitsu Awano, Takashi Sato. Efficient transistor-level timing yield estimation via line sampling. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016. pages 115, ACM, 2016. [doi]
@inproceedings{AwanoS16, title = {Efficient transistor-level timing yield estimation via line sampling}, author = {Hiromitsu Awano and Takashi Sato}, year = {2016}, doi = {10.1145/2897937.2898016}, url = {http://doi.acm.org/10.1145/2897937.2898016}, researchr = {https://researchr.org/publication/AwanoS16}, cites = {0}, citedby = {0}, pages = {115}, booktitle = {Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016}, publisher = {ACM}, isbn = {978-1-4503-4236-0}, }