Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

Stéphane Badel, Yusuf Leblebici. Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 1871-1874, IEEE, 2007. [doi]

@inproceedings{BadelL07,
  title = {Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage},
  author = {Stéphane Badel and Yusuf Leblebici},
  year = {2007},
  doi = {10.1109/ISCAS.2007.378280},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378280},
  tags = {logic, design},
  researchr = {https://researchr.org/publication/BadelL07},
  cites = {0},
  citedby = {0},
  pages = {1871-1874},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
  publisher = {IEEE},
}